The present invention relates to semiconductor devices and, more particularly, to methods of forming metal patterns in openings in semiconductor devices.
A demand exists for semiconductor devices that have a high integration density, low power consumption and which are capable of high speed operation. To meet these requirements, various methods of forming patterns such as, for example, wiring patterns or contact plugs, have been proposed which form the patterns using a low resistivity metal. By employing low resistivity metal patterns, the operation speed of the semiconductor device can be improved and power consumption may be reduced. In addition, the use of low resistivity metal may permit the use of metal wiring patterns having reduced widths, which can facilitate increased device integration density.
Metal patterns can be formed by depositing a metal layer on a substrate or semiconductor layer and then patterning the deposited metal layer. The patterning may be performed by using a photolithography process to define a mask pattern and an etching process that etches the metal layer using the mask pattern as an etch mask. The metal patterns may alternatively be formed by a damascene method. For instance, a metal layer may be formed to fill an opening in an interlayer dielectric layer, and the metal layer may then be planarized to expose the dielectric layer. However, when the metal patterns are formed in a opening in an interlayer dielectric layer, various problems may arise that can degrade various characteristics of a semiconductor device. For example, a metal layer may not completely fill the opening in the interlayer dielectric layer, thereby forming a void. Even worse, a metal layer formed in a opening in an interlayer dielectric layer may not form an electrical connection with an underlying layer or structure. Such problems may degrade the performance of a semiconductor device or even cause a failure thereof. As the degree of device integration increases, the aspect ratio of the opening in the interlayer dielectric layer also tends to increase. Such higher aspect ratios may aggravate the aforementioned void and/or electrical disconnection problems.